1. Field of the Invention
The present invention relates to a timing recovery apparatus and a diversity communication apparatus using the timing recovery apparatus and, more particularly, the present invention is applicable to a demodulator for use in a digital wireless communication apparatus based on PSK (Phase Shift Keying).
2. Description of Prior Art
A timing recovery apparatus for a demodulator of a digital wireless communication apparatus based on PSK is disclosed on JP-A 6/252965. The disclosed timing recovery apparatus uses a phase detecting section for initial pull-in that detects a clock phase by using a preamble pattern and a phase detecting section for steady state based on zero cross detecting that detects lead or lag of a clock phase. Various schemes for conventional diversity communication apparatuses are described in "Basics of Mobile Communication," Chapter 7, edited by Institute of Electronics, Information and Communication Engineers of Japan, published by Corona Publishing, for example.
FIG. 50 shows a conventional diversity receiving apparatus including the above-mentioned timing recovery apparatus. For simplicity of description, let the number of branches K of the diversity of this diversity receiving apparatus be 2. In the figure, reference numerals 1A and 1B indicate antennas, 2A and 2B indicate detecting sections, 3A and 3B indicate sampling sections, 4 indicates a diversity section, 5 indicates a timing recovery section, 6 indicates a Nyquist point extracting section, 7a indicates a Nyquist point data output terminal, 7b indicates a burst gate input terminal, 7c indicates a frame synchronization signal input terminal. In the timing recovery section 5, reference numeral 10 indicates phase detecting section for initial pull-in (hereinafter, it is called as an initial pull-in phase detecting section), 11 indicates a phase detecting section for steady state (hereinafter, it is called as a steady state phase detecting section), 12 indicates a filtering section for initial pull-in (hereinafter, it is called as an initial pull-in filtering section), 13 indicates a filtering section for steady state (hereinafter, it is called as a steady state filtering section), 14 indicates a phase control selecting section, and 15 indicates a phase controlling section.
FIG. 51 shows a constitution of the initial pull-in phase detecting section 10, in which reference numerals 16 and 17 indicate registers, 18 indicates a subtractor, 10a indicates a received phase data input terminal, 10b indicates a regenerated double frequency clock input terminal, and 10c indicates a differential data output terminal. FIG. 52 shows a constitution of the initial pull-in filtering section 12, in which reference numeral 20 indicates a serial-parallel converter, 21 indicates an integrator, 22 indicates integration controlling section, 23 indicates a ROM, 24 indicates a register, 12a indicates a differential data input terminal, 12b indicates a regenerated 1/2 frequency clock input terminal, 12c indicates a regenerated clock input terminal, 12d indicates a burst gate input terminal, 12e indicates a timing phase difference data output terminal, and 12f indicates a timing phase difference data calculation complete signal output terminal. In the integrator 21, reference numerals 26A and 26B indicates multiplier, 27A and 27B indicate adders, 28A and 28B indicate registers, 29A and 29B indicate dividers. In the integration controlling section 22, reference numeral 30 indicates an AND gate, 31 indicates an inverter, 32 indicates an up counter, and 33 indicates a comparator.
FIG. 53 shows a constitution of the steady state phase detecting section 11, in which reference numeral 11a indicates a received phase data input terminal, 34 indicates a polar-coordinate converter, 35A and 35B indicate zero-cross detectors, 36 indicates a zero-cross signal synthesizing section, 11b indicates a LEAD signal output terminal, and 11c indicates CROSS signal output terminal. FIG. 54 shows a constitution of the zero-cross detectors 35A and 35B, in which reference numeral 35a indicates a data input terminal, 35b indicates a regenerated clock input terminal, 37A, 37B, 37C and 37D indicate registers, 38 indicates an inverter, 39A and 39B indicate exclusive OR gates, 35c indicates an LEAD signal output terminal, and 35d indicates a QCROSS signal output terminal.
FIG. 55 shows a constitution of the steady state filtering section 13, in which a reference numeral 13a indicates frame synchronization signal input terminal, 13b indicates a phase control complete signal input terminal, 13c indicates a LEAD signal input terminal, 13d indicates a CROSS signal input terminal, 13e indicates a burst gate input terminal, 13f indicates a regenerated clock input terminal, 40 indicates a selector, 41 indicates a 1-bit shifter, 42 indicates an UP/DOWN counter, 43A and 43B indicate comparators, 44 indicates an OR gate, 13g indicates an UP signal output terminal, and 13h indicates a DOWN signal output terminal.
FIG. 56 shows a constitution of the phase control selecting section 14, in which reference numeral 14a indicates a timing phase difference data calculation complete signal input terminal, 14b indicates an UP signal input terminal, 14c indicates a DOWN signal input terminal, 14d indicates a timing phase difference data input terminal, 45 indicates an UP/DOWN data generating section, 46 indicates a gate circuit, and 14e indicates a phase control data output terminal. FIG. 57 indicates a constitution of the phase controlling section 15, in which reference numeral 15a indicates a phase control data input terminal, 15b indicates a regenerated 2.sup.m times (for example 32 times) frequency clock input terminal, 47A and 47B indicate comparators, 48 indicates an AND gate, 49 indicates an m-bit up counter, 50 indicates a 1/2 divider, 51A and 51B indicate inverters, 15c indicates a regenerated 1/2-times frequency clock output terminal, 15d indicates a regenerated clock output terminal, 15e indicates a regenerated double frequency clock output terminal, 15f indicates a regenerated 16-times frequency clock output terminal, and 15g indicates a phase control complete signal output terminal.
The operations of the above-mentioned conventional diversity receiving apparatus will be described. First, the operations of the diversity receiving apparatus in its entirety will be described. In this example, for reduction in size and power consumption, the demodulator of the receiving apparatus for digital mobile communication operates by using only phase information, discarding amplitude information. That is, the demodulator operates by using only a baseband receive phase signal obtained by detecting the carrier signal that passed the limiter. Also, in this example, delay detecting based on .pi./4 shift QPSK (Quadrature PSK) is used for demodulation. In the conventional diversity receiving apparatus, two antennas 1A and 1B receive a PSK signal. Two detecting sections 2A and 2B detect the received signal to output an analog baseband receive phase signal and a receive signal power. The detecting sections 2A and 2B are each composed of a limiter, a bandpass filtering section, mixer, and other analog devices.
The sampling sections 3A and 3B each oversample each analog baseband receive phase signal at a double frequency double of a symbol frequency to output quantized baseband receive phase data. Here, it is assumed that the phase resolution of the baseband receive phase data be 5 bits. The diversity section 4 delay-detects the baseband phase signals outputted from the sampling sections 3A and 3B. An automatic frequency controlling section in the diversity section 4 removes a carrier frequency deviation from each baseband phase signal. Then, the diversity section 4 performs signal synthesis such as selective synthesis, equivalent gain synthesis or maximum ratio synthesis described in the above-mentioned document "Basics of Mobile Communication" by using the received signal power and the two pieces of delay-detected baseband receive phase data outputted from the detecting sections 2A and 2B to output the synthesized baseband receive phase data to the timing recovery section 5 and the Nyquist point extracting section 6.
The timing recovery section 5 outputs a regenerated double frequency clock to be used by the sampling sections 3A and 3B. The timing recovery section 5 controls the clock phase such that the double regenerated clock samples Nyquist points of the baseband receive phase data every two samples. Consequently, the Nyquist point of the baseband receive phase data after delay detection also appears, every two samples, in the baseband receive phase data after synthesis outputted from the diversity section 4. The Nyquist point extracting section 6 extracts the Nyquist point coming from the baseband receive phase data from the synthesized baseband receive phase data outputted from the diversity section 4. Further, the extracting section polar-coordinate converts the extracted phase data to output in-phase Nyquist point data and orthogonal Nyquist point data.
The following describes the above-mentioned operations with reference to the timing chart of FIG. 58. The curves of (A) and (C) of FIG. 58 indicate the baseband receive phase data detected by the detecting sections 2A and 2B. The baseband receive phase data are the data obtained by performing .pi./4 shift QPSK on the data pattern in which "00" and "10" repeat by the mapping shown in FIG. 59. For simplicity of description, no carrier frequency deviation is given to the baseband receive phase data. When the data pattern in which "00" and "01" repeat is modulated by .pi./4 shift QPSK, the phase fluctuates from 0 to .pi./4 or from .pi./4 to 0 at a symbol interval. However, the baseband receive phase data indicating this phase jitter is distorted by the influence of noise or phasing as indicated by the curves of (A) and (C) of FIG. 58. A tiny circle in the figure shows a Nyquist point, of which phase originally indicates 0 and .pi./4. However, by the influence of noise and phasing, the phase at Nyquist point takes a different value at a position at which the received signal power outputted from the detecting sections 2A and 2B drops. The received signal power outputted from the detecting sections 2A and 2B are shown in (B) and (D) of FIG. 58.
The sampling sections 3A and 3B sample the baseband receive phase data (A) and (C) respectively by the regenerated double frequency clock outputted from the timing recovery section 5 shown in (F) of FIG. 58. The sampled data are indicated by vertical lines in (A) and (C) of FIG. 58. The diversity section 4 delay-detects the sampled baseband receive phase data shown in (A) and (C) of FIG. 58. If not affected by noise or phasing, the delay-detected Nyquist point phase data show .pi./4 and -.pi./4 alternately. Then, the diversity section 4 performs signal synthesis by selective synthesis, equivalent gain synthesis or maximum ratio synthesis by using two pieces of delay-detected baseband receive phase data and the received signal power (B) and (D), outputting the delay-detected baseband receive phase data after synthesis indicated by vertical lines in (E) of FIG. 58.
The timing recovery section 5 uses the synthesized delay-detected baseband receive phase data (E) to control the clock phases of the regenerated double frequency clock (F) of FIG. 28 and the regenerated clock (G) such that the rise position of each of these clocks comes to a Nyquist point. In the example of FIG. 58, the phase difference between the rise of the Nyquist point and the regenerated clock is .pi./2 initially, but as time goes by, this phase difference converges to zero gradually. The Nyquist point extracting section 6 extracts the delay-detected base band receive phase data (E) at the rise of the regenerated clock (G) as Nyquist point data to output the same as in-phase and orthogonal Nyquist point data shown in (H) and (I) of FIG. 58. Consequently, in the first half of the timing chart, the Nyquist point extracting section 6 outputs the data that are deviated from the Nyquist point by .pi./2 as the Nyquist point data; in the last half of the timing chart, the extracting section 6 can output the inherent Nyquist point data by the clock phase control performed by the timing recovery section 5.
The operation of the timing recovery section 5 will be described. The present diversity apparatus receives burst data as shown in FIG. 60. The timing recovery section 5 uses a data pattern that repeats "01" and "10" called a preamble pattern in the head of the burst data to calculate a timing phase difference and, at the same time, performs the clock phase initial pull-in controlling. The calculation of the timing phase difference is performed by the initial pull-in phase detecting section 10 and the initial pull-in filtering section 12. After the clock phase initial pull-in controlling, the timing recovery section 5 performs a timing phase following operation by using a random pattern (including a unique word pattern for frame synchronization) shown in FIG. 60. The timing phase following operation is performed by the steady state phase detecting section 11 and the steady state filtering section 13.
First, the clock phase initial pull-in control operation will be described. The initial pull-in phase detecting section 10 uses the synthesized delay-detected baseband receive phase data outputted from the diversity section 4 to output differential data that provides a phase detection signal. The initial pull-in filtering section 12 integrates the differential data. The initial pull-in filtering section 12 outputs the timing phase difference data indicating the phase difference between Nyquist point and regenerated clock and the timing phase difference data calculation complete signal indicating the completion of the timing phase difference data calculation. The initial pull-in phase detecting section 10 and the initial pull-in filtering section 12 calculate the timing phase difference by using the preamble pattern. It should be noted that the timing phase difference cannot be calculated from a random pattern in which data changes irregularly.
The operations of the initial pull-in phase detecting section 10 and the initial pull-in filtering section 12 will be described with reference to the timing chart of FIG. 61. In the baseband receive phase data having the preamble pattern entered from the input terminal 10a of the initial pull-in phase detecting section 10, the Nyquist points indicated by a tiny circle take values of 3.pi./4 and -.pi./4 alternately unless unless affected by noise or the like as shown in (A) of FIG. 61. The registers 16 and 17 that operate on the regenerated double frequency clock entered from the input terminal 10b perform re-timing on the baseband receive phase data to delay the same by one symbol as shown in (B) of FIG. 61. The subtractor 18 subtracts the baseband receive phase data delayed by one symbol from the baseband receive phase data to generate differential data as shown in (C) of FIG. 61 and output the same from the output terminal 10c. Therefore, the differential data at the Nyquist points indicate the .pi. and -.pi. values alternately. It is assumed here that the phase difference between Nyquist point and regenerated clock be 7.pi./4 as shown in (E) of FIG. 61. In this case, the vertical line in (C) of FIG. 61 provides the data sampled by the regenerated double frequency clock.
The differential data entered from the input terminal 12a are serial-parallel converted by the serial-parallel converter 20 into data of two sequences in which even-number data and odd-number data are separated from each other. The multipliers 26A and 26B the data of two sequences by 1 when the regenerated 1/2 frequency clock coming from the input terminal 12b is logic "1" or -1 when the same is logic "0" shown in (F) of FIG. 61. Then, the data of two sequences are converted to data indicated by vertical dotted lines shown in (C) of FIG. 61. As shown in (C) of FIG. 61, let the even-number data sequence after multiplication be G.sub.i (i=1, 2, 3, . . . ) and the odd-number data sequence after multiplication be H.sub.i (i=1, 2, 3, . . . ) as shown in (C) of FIG. 61. The two data sequence G.sub.i and H.sub.i are accumulated by J times (J.gtoreq.2) by two accumulators composed of adders 27A and 27B and registers 28A and 28B respectively.
The clock to operate the two accumulators by J times is realized by performing a logical product operation by the AND gate 30 between the regenerated clock and the gate signal that indicates logic "1" during J symbol period at input of the preamble pattern. The comparator 33 indicates logic "0" when the output of the up counter 32 is less than J. The up counter 32 starts counting at the rise of the burst gate signal entered from the input terminal 12d in the timing shown in FIG. 60. The gate signal is generated by inverting the output of the comparator 33 that compares the output of the up counter 32 with J.
The two data sequence G.sub.i and H.sub.i accumulated by J times are divided by J in the dividers 29A and 29B respectively. Therefore, mean value GA of G.sub.1 through G.sub.J and mean value HA of H.sub.1 through H.sub.J are obtained. The GA and HA are entered in ROM 23, from which the timing phase difference is outputted based on the input-output relationship shown in FIG. 62. As described above, the output of the comparator 33 rises from logic "0" to "1" when the output of the up counter 32 exceeds J. The timing phase difference can be obtained at this point of time, the output of the comparator 33 is outputted from the output terminal 12f as the timing phase difference data calculation complete signal. In addition, the output of the ROM 23 is latched in the register 24 by the output of the comparator 33. The latched data are outputted from the output terminal 12e as the timing phase difference data.
The following describes the timing phase following operation to be performed by the steady state phase detecting section 11 and the steady state filtering section 13 after the clock phase initial pull-in control. Following the initial pull-in control, the steady state phase detecting section 11 and the steady state filtering section 13 perform phase control. The steady state phase detecting section 11 uses the synthesized delay-detected baseband receive phase data outputted from the diversity section 4 and generates a LEAD signal that indicates whether the current timing phase is advancing or lagging and a CROSS signal that indicates that the LEAD signal is valid. In what follows, the operation of the steady state phase detecting section 11 will be described. The delay-detected baseband receive phase data coming from the input terminal 11a is converted by the polar-coordinate converter into IDATA that indicates an in-phase component and QDATA that indicates an orthogonal component. The IDATA and the QDATA are entered in the zero-cross detectors 35A and 35B respectively.
The registers 37A and 37B in the zero-cross detector 35A of FIG. 54 sample the IDATA entered from the input terminal 35a at the rising and falling of the regenerated clock. Here, let sample data of the IDATA at the falling edge of the regenerated clock obtained by the inverter 38 and the register 37A be Z.sub.n (n=1, 2, 3, . . . ), sample data of the IDATA at the rising edge obtained by the register 37B be N.sub.n (n=1, 2, 3, . . . ), and sample data of the IDATA at the rising edge delayed by one symbol obtained by the register 37C be N.sub.(n-1) (n=1, 2, 3, . . . ), then the zero cross of the data occurs when the following relation is established as shown in FIGS. 63(A) and 63(B): EQU N.sub.n .times.N.sub.(n-1) &lt;0 (1)
In this case, if EQU N.sub.n .times.Z.sub.n &gt;0 (2)
indicating that the clock phase is advancing before the Nyquist point as shown in FIG. 63(A). EQU If N.sub.n .times.Z.sub.n &lt;0 (3)
indicating that the clock phase is lagging behind the Nyquist point as shown in FIG. 63(B).
In the above-mentioned example, DPLL (Digital Phase Locked Loop) is used for clock phase control. Sample data is used as one-bit decision data. The exclusive OR gate performs an exclusive OR operation between the data N.sub.n and the data N.sub.(n-1) which is one symbol before the data N.sub.n to output a signal that indicates the detection of data zero cross. When the zero cross is detected, an ICROSS signal of logic "1" is outputted from the output terminal 35d. The ILEAD signal that indicates the lead or lag of the clock phase is obtained by performing an exclusive OR operation between the data Z.sub.n (n=1, 2, 3, . . . ) re-timed at the rising of the regenerated clock by the register 37C and N.sub.n (n=1, 2, 3, . . . ) outputted from the register 37B. Namely, the output of the exclusive OR gate 39A indicates the ILEAD signal. If the clock phase is advancing, the ILEAD signal of logic "0" is outputted from the output terminal 35c; if the clock phase is lagging, the ILEAD signal of logic "1" is outputted from the output terminal 35c.
The operation of the zero-cross detector 35B with QDATA inputted is generally the same as that of the zero-cross detector 35A. The zero-cross detector 35B outputs the QCROSS signal that indicates whether QDATA zero cross occurred or not and the QLEAD signal that indicates whether the clock phase is advancing or lagging. The zero-cross signal synthesizing section 36 generates the LEAD signal and the CROSS signal from the ILEAD, ICROSS, QLEAD, and QCROSS signals to output the LEAD signal from the output terminal 11b and the CROSS signal from the output terminal 11c. The LEAD signal and the CROSS signal are outputted according to the condition of FIG. 64. The LEAD signal is obtained by a logical OR operation between the ILEAD signal and the QLEAD signal. The CROSS signal is also basically obtained by a logical OR operation between the ICROSS signal and the QCROSS signal; however, if the ICROSS signal and the QCROSS signal are both logic "1's" and the ILEAD signal and the QLEAD signal have different values, then the CROSS signal is set to logic "0".
The steady state filtering section 13 of FIG. 55 averages the LEAD signal coming from the input terminal 13c if the CROSS signal coming from the input terminal 13d is logic "1". Then, if the filtering section 13 determines that the timing phase is lagging, the filtering section 13 outputs an UP signal that leads the timing phase from the output terminal 13g; if the filtering section 13 determines that the timing phase is advancing, the filtering section 13 outputs a DOWN signal that delays the timing phase from the output terminal 13h. The averaging is implemented by the UP/DOWN counter 42. The UP/DOWN counter 42 operates in the period of the regenerated clock entered from the input terminal 13f. The UP/DOWN counter 42 is enabled when the burst gate signal of FIG. 60 is entered as logic "1" from the input terminal 13e and the CROSS signal that indicates the detection of zero cross is logic "1".
FIG. 65 shows the timing chart of the operation of the steady state filtering section 13. The UP/DOWN counter is initially set to a value Nx. Then, the UP/DOWN counter down-counts if the LEAD signal indicates a phase lead or up-counts if the LEAD signal indicates a phase lag. The output of the UP/DOWN counter 42 is compared with 2Nx in the comparator 43A and with 0 in the comparator 43B. Detecting a match, these comparators each output logic "1" each. Value 2Nx is generated by one-bit shifting Nx by the bit shifter 41. When the counter value reaches 2Nx as shown in (a) of FIG. 65, the UP signal of logic "1" is outputted from the comparator 43A to the output terminal 13g. When the count value reaches 0 as shown in (b) of FIG. 65, the DOWN signal of logic "1" is outputted from the comparator 43B to the output terminal 13h.
The signal of logic "1" coming from the comparator 43A or 43B is also a load signal to the UP/DOWN counter 42. Therefore, when the signal of logic "1" is outputted from the comparator 43A or 43B, Nx is set again to the UP/DOWN counter. The first loading of Nx is performed by the phase control complete signal entered from the phase controlling section 15 to the input terminal 13b, this signal indicating that the timing phase control has been completed. The filtering section for steady state 13 uses the frame synchronization signal entered from the input terminal 13a to determine whether the current point is in phase pull-in state or steady state. In the phase pull-in state, high-speed pull-in is required, so that, in the phase pull-in state, the selecting section (SEL) 40 sets Nx to a relatively small value N.sub.1 and, in the steady state, a low jitter is required, so that the selecting section sets Nx to a relatively large value N.sub.2.
The phase control selecting section 14 shown in FIG. 56 outputs the phase control data that indicates a controlled quantity from the output terminal 14e. In this example, the resolution of the phase control is 1/32 symbol. Therefore, the timing phase data of 0 to 2.pi. and the phase control data of 0 to 2.pi. outputted from the initial pull-in phase filtering section 12 are both represented in 0 to 31. The phase control by the UP signal and the DOWN signal is performed at every 1/32 symbol. The UP signal entered from the input terminal 14b and the DOWN signal entered from the input terminal 14c are entered in the UP/DOWN data generating section 45.
The UP/DOWN data generating section 45 outputs "15" when the UP signal is logic "1", outputs "17" when the DOWN signal is logic "1", and outputs "16" otherwise. The gate circuit 46 holds the phase control data to "16" until the calculation of the timing phase data by the initial phase pull-in operation is completed. When the timing phase data is entered from the input terminal 14d upon completion of the calculation of the timing phase data, the gate circuit 46 converts the timing phase data "0 to 15, 16 to 31" to "16 to 31, 0 to 15" to output the result as the phase control data. After completion of the timing phase data calculation, the gate circuit 46 outputs the data outputted from the UP/DOWN data generating section 45 as the phase control data. The completion of the timing phase data calculation can be known by the timing phase data calculation complete signal entered from the input terminal 14a.
In the phase controlling section 15 of FIG. 57, the UP/DOWN counter 49 up-counts by a fixed clock that is 32 times the symbol frequency entered from the input terminal 15b . The UP counter 49 outputs a count value in 5 bits, the most significant bit being outputted from the output terminal 15d as the regenerated clock. The counter outputs of the remaining 4 bits except for the most significant bit are inverted by the inverter 51A through 51B to be a regenerated double frequency clock through regenerated 16-times frequency clock. These clocks are outputted from the output terminals 15e through 15f respectively. The 1/2 divider divides the regenerated clock by 2 to generate a regenerated 1/2 frequency clock, which is outputted from the output terminal 15c.
The 5-bit output value of the UP counter 49 is compared with "16" in the comparator 47A. The comparator 47A outputs logic "1" if the counter output value matches "16". The output of the comparator 47A is used as a load signal to the UP counter 49. When the load signal is logic "1", the UP counter 49 loads the phase control data entered from the input terminal 15a . If the phase control data takes the value of "16" that indicates that the phase control data is in the uncontrolled state, "16" is loaded when the count value of the UP counter 49 is "16", so that the count value does not become discontinuous. Consequently, the phase change of the regenerated clock does not occur.
If the clock phase is advancing, the phase control data becomes "17" by the DOWN signal. Therefore, as shown in FIG. 66(A), when the count value of the UP counter 49 reaches "16", "17" is loaded in the UP counter 49. As a result, the clock phase is delayed. If the clock phase is lagging, the phase control data becomes "17" by the UP signal. Therefore, as shown in FIG. 66(B), the count value of the UP counter 49 reaches "16" "15" is loaded in the UP counter. As a result, the clock phase is led.
At the time of initial phase pull-in, the phase control data take a value 0 to 31, so that, when the count value of the UP counter reaches "16", a value 0 to 31 is loaded. As a result, clock phase pull-in is realized. FIG. 67 shows an example in which clock phase pull-in is performed when the initial phase difference is 3.pi./2. By the initial pull-in detecting section 10 and the initial pull-in filtering section 12, the phase difference 3.beta./2 is outputted as timing phase difference data "24". The timing phase difference data "24" is converted to phase control data "8". Then, when the count value of the UP counter 49 reaches "16", "8" is loaded.
When the phase control has been completed, the phase control complete signal for instructing the setting of the value of the UP/DOWN counter 42 to Nx is outputted from the output terminal 15g. The comparator 47B compares the phase control data with "16". If a match found, the comparator 47B outputs logic "1". The AND gate 48 performs a logical AND operation between the output of the comparator 47B and the load signal. The output of the AND gate becomes the phase control complete signal. Thus, the timing phase synchronization by the timing recovery section 5 is performed.
The conventional timing recovery section 5 calculates the timing phase difference by using 10 to 20 symbols of the preamble data located in the head of burst data to perform initial phase control. The time required for the initial phase control is a time from starting the signal entry to the calculation of the timing phase difference. After the initial phase control, the timing recovery section 5 performs a phase following operation by using a random pattern. Therefore, the initial phase control cannot be performed if the position of the preamble pattern is not known when a portable radio terminal is powered on in which the timing when burst data come has not yet been established, or at the time of recovery from such line disconnection as blockage, for example. In this case, the phase detecting section for steady state 11 and the filtering section for steady state 13 which use a random pattern perform timing phase pull-in. However, the phase pull-in using the random pattern performed by the steady state phase detecting section 11 and the steady state filtering section 13 is performed based on the lead or lag of the timing phase. Consequently, even if a noiseless transmission path is assumed and Nx in the steady state filtering section 13 is set to "2", it takes as long a time as equivalent to about 100 symbols until completion of the timing phase pull-in.
In the conventional diversity receiving apparatus, the outputs of the detecting sections 2A and 2B are sampled by the sampling sections 3A and 3B, the results being synthesized by the diversity section 4. Because the detecting sections 2A and 2B are implemented by analog devices, a difference occurs between the signal delay time in the detecting section 2A and that in the detecting section 2B. Depending on analog devices used, a delay time difference of about .pi./2 in terms of phase may occur. If there is a delay time difference between the two detecting sections 2A and 2B, selective synthesis, equivalent gain synthesis or maximum ratio synthesis is performed in the diversity section 4 with the Nyquist point positions of the two signals offset from each other. If equivalent gain synthesis or maximum ratio synthesis is performed on the two signals in a phase relationship in which the Nyquist point positions are largely offset, the synthesized signals are distorted, deteriorating bit error rate characteristic and synchronization characteristic. As for selective synthesis performed in the similar condition, the Nyquist point positions are offset at signal switching, thereby temporarily causing a timing phase difference, resulting in deteriorated bit error rate characteristic and synchronization characteristic.